1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a synchronous semiconductor memory device employing a pipeline operation that consumes less power.
2. Description of the Background Art
A synchronous semiconductor memory device employing a pipeline operation is disclosed, for example, in U.S. Pat. No. 5,838,631, which prevents conflict of read data with write data at a data terminal to speed up the operation.
FIG. 7 is a block diagram illustrating a configuration of a conventional synchronous semiconductor memory device 5000 employing the pipeline operation, disclosed in the above-mentioned U.S. Pat. No. 5,838,631.
Referring to FIG. 7, semiconductor memory device 5000 includes: a terminal group 110 externally sending and receiving data, a clock signal and a control signal; a memory array circuit 120 for storing the externally sent and received data in a memory cell; a control circuit 130 for controlling reading/writing operations with memory array circuit 120 and data input/output at terminal group 110 according to the externally supplied control signal; and a write data retaining circuit 140 and a write address retaining circuit 150 for temporarily retaining, respectively, write data of which writing is designated and its corresponding address. Semiconductor memory device 5000 is able to temporarily retain two pieces of write data by write data retaining circuit 140 and write address retaining circuit 150. Accordingly, in semiconductor memory device 5000, sending and receiving of input/output data at a data terminal is performed 2 clock cycles later than the input of the corresponding address signal.
Data terminal group 110 receives a chip select signal CS# for driving a chip into a selected state, a clock enable signal CKE# for selecting an enabled/disabled state of the chip, a reference clock signal CLK, an address signal ADD consisting of address bits A0-An, and a write enable signal WE#. Data terminal group 110 includes a data terminal 19 performing data input/output.
An address register AReg.0 operates as an address buffer for taking in an address signal in response to each activation edge of reference clock signal CLK, and outputs an input address AR0 in each clock cycle.
Memory array circuit 120, having therein a plurality of memory cells arranged in rows and columns as storage elements, responds to a control signal output from control circuit 130 for reading data out of or writing data into a memory cell selected by an address signal. Although not shown, memory array circuit 120 includes memory cells arranged in rows and columns, a decoder for selecting a memory cell corresponding to an address signal, an input/output circuit for writing and reading data to and from a memory cell, and others. These features are collectively shown as memory array circuit 120 in FIG. 7. In other words, memory array circuit 120 responds to a control signal supplied from control circuit 130 to its signal terminals READ# and WRITE#, and performs a reading operation or a writing operation of data for the memory cell that corresponds to the address signal input to address terminal ADR. The write data for use in the writing operation are input from data terminal IN, and the read data being output from a memory cell by the reading operation are output from data terminal OUT.
When the chip is in an enabled state, i.e., when the clock enable signal is in an active state (at an L level), control circuit 130 responds to each activation edge of reference clock signal CLK and takes in the signal levels of control signals CS# and WE# at the relevant clock cycle, while retaining their signal levels of one clock cycle before.
In response to the combination of the signal levels, control circuit 130 generates control signals WB1, WB2, RB and the like, which are updated in response to each activation edge of reference clock signal CLK. Control signal WB1 is activated when the chip is in a selected state and the writing operation is designated by write enable signal WE# in the relevant clock cycle. Control signal RB is activated when the chip is in a selected state and the reading operation is designated by write enable signal WE# in the relevant clock cycle. Control signal WB2 is a signal which retains the signal level of control signal WB1 one clock cycle before, and it designates which should be performed at data terminal 19, data input or data output, at the next activation edge of reference clock signal CLK.
Write data retaining circuit 140 takes in and temporarily retains write data input to data terminal 19 by two register circuits DReg.1 and DReg.2 that are enabled in response to control signal WB2.
Write address retaining circuit 150 receives input address AR0 from address register AReg.0, and retains storage addresses AR1 and AR2 that correspond to the write data stored in write data retaining circuit 140 by two register circuits Areg.1 and Areg.2, that are enabled in response to the output of a logic gate 11 that outputs an OR logical operation result of control signal WB1 and clock enable signal CKE#.
An address matching circuit 160 includes address comparison circuits 30 and 32 which perform matching of input address AR0 with respective storage addresses AR1 and AR2 stored in address retaining circuit 150. Address comparison circuit 30 activates an address match signal EQ1 (to an H level) when input address AR0 matches storage address AR1. Address comparison circuit 32 activates an address match signal EQ2 (to an H level) when input address AR0 matches storage address AR2. If at least one of the two signals is activated, it means that an address corresponding to the write data that have been input from the data terminal but not yet written into memory array circuit 120 is now a target for the reading operation. In this case, there is a need to set a data path which permits the stored write data to be directly read out from the data terminal, instead of read data being directly output from the memory array circuit.
FIG. 8 is a block diagram illustrating configurations of address comparison circuits 30 and 32.
In FIG. 8, a configuration corresponding to each bit of address signal ADD is shown. Referring to FIG. 8, bits A0 to An of address signal ADD are supplied to address input terminals 4-0 to 4-n, respectively. Connected to each address input terminal are three address registers, which correspond to address registers AReg.0 to AReg.2 shown in FIG. 7. For example, address registers AReg.00, AReg.10 and AReg.20 are provided for address signal bit A0 input to address input terminal 4-0. As seen in FIG. 7, address register AReg.00 receives clock enable signal CKE# as its operation enable signal, and address registers AReg.10 and AReg.20 each receive the output of logic gate 11 as its operation enable signal. Each bit of the address signal is provided with a similar register circuit group. With such a configuration, signals AR00 to AR0n are obtained for respective bits corresponding to input address AR0 as shown in FIG. 7, and signals AR10 to AR1n and AR20 to AR2n are also obtained for respective bits corresponding to storage addresses AR1 and AR2.
Address comparison circuit 30 has address comparison units COMP10 to COMP1n. Address comparison unit COMP10 includes: a logic gate 52 that receives AR00 and AR10 to output their NAND logical operation result; a logic gate 53 that receives inverted signals of AR00 and AR10 to output their AND logical operation result; an inverter 54 that inverts an output of logic gate 53; and a logic gate 55 that receives inverted signals of respective outputs of logic gate 52 and inverter 54 to output their OR logical operation result. The output of logic gate 52 attains an L level when AR00 and AR10 are both at an H level and match with each other. Similarly, the output of logic gate 53 attains an H level when AR00 and AR10 are both at an L level and match with each other, and in response, the output of inverter 54 attains an L level.
Thus, when the signal levels of AR00 and AR10 match, one input of logic gate 55 attains an L level, and the output of logic gate 55 attains an H level. Each address comparison unit has a similar configuration. Address comparison unit COMP1i (i is an integer between 0 and n) detects a match of AR0i and AR1i. 
Address comparison circuit 30 further includes: a logic gate 56 that receives an output of each address comparison unit; and an inverter 57 that inverts an output of logic gate 56. Logic gate 56 receives respective outputs of address comparison units COMP10 to COMP1n, and outputs their NAND logical operation result. Therefore, address match signal EQ1 attains an H level when every bit AR00-AR0n of the input address matches its corresponding bit AR10-AR1n of storage address AR1.
Address comparison circuit 32, though detailed configuration of which is not shown, has a configuration similar to that of address comparison circuit 30. Address comparison circuit 32 compares respective bits AR00 to AR0n of input address AR0 with corresponding bits AR20 to AR2n of storage address AR2 and, when all the bit pairs match completely, activates an address match signal EQ2 (to an H level).
Returning to FIG. 7, a data path select circuit 170 includes data path setting circuits 171 to 174, which form data paths for directly reading out write data stored in write data retaining circuit 140 or write data input at the data terminal at a relevant clock cycle, dependent on the comparison result of address matching circuit 160. Data path setting circuits 171 to 174 set paths 1 to 4, respectively, according to the combination of the comparison result of address matching circuit 160 and control signal WB2.
Read data selected by data path select circuit 170 are supplied to the D terminal of a read data register DReg.3. Read data register DReg.3 is enabled, in response to control signal RB, at a clock cycle in which the chip is in a selected state and a reading operation is designated. It then outputs data that have been input to its D terminal from data path select circuit 170 to its Q terminal in response to an activation edge of reference clock signal CLK. When an output enable signal OE# is in an active state, the data that were output to Q terminal are output via a buffer circuit 28, which is controlled according to the combination of control signals CS2 and WB2. The data are then output from data terminal 19 in response to an activation edge of reference clock signal CLK at a clock cycle in which a data output is designated to the data terminal, i.e., at a clock cycle that is two clock cycles after the clock cycle in which the reading operation was designated.
With the configuration as described above, semiconductor memory device 5000 provides its data input system with a latching capability, so that write data are temporarily retained before being written into the memory array circuit. Thus, the reading/writing operations for the memory cell array and the data input/output operations at the data terminal can be performed independent of each other, whereby high-speed data transfer is accomplished based on the pipeline system.
FIG. 9 is a timing chart illustrating the operation of the conventional semiconductor memory device 5000. In FIG. 9, clock enable signal CKE#, chip select signal CS# and output enable signal OE# are all assumed to be in an active state (at an L level) to illustrate a normal operation mode. FIG. 9 includes all the possible combinations of reading/writing operations within four clock cycles. Write enable signal WE# designates, at each cycle time from cycle time t1 through cycle time t19, a series of operations of W (write operation) WWWR (read operation) RRRWWRWRRWRWWW.
Referring to FIG. 9, clock cycles t1 to t21 are defined in response to respective activation edges of reference clock signal CLK. Address signal ADD is input at an activation edge of clock signal CLK in each clock cycle. Write enable signal WE# is set at an L level in a clock cycle in which a writing operation is designated, and set at an H level in a clock cycle in which a reading operation is designated.
Read data or write data corresponding to the input address are output from or input to data terminal 19 two clock cycles later. For example, input data D1 to D4 corresponding to input addresses A1 to A4 in clock cycles t1 to t4 in each of which the writing operation is designated are input to the data terminal two clock cycles later, i.e., in clock cycles t3 to t6. Read data D (A5) to D (A8) corresponding to input addresses A5 to A8 in clock cycles t5 to t8 in each of which the reading operation is designated are output from the data terminal two clock cycles later in clock cycles t7 to t10.
Address register AReg.0 takes in an address signal received at the address input terminal 4 at each clock cycle as input address AR0. Address registers AReg.1 and AReg.2 sequentially take in and transfer the input addresses in response to activation of control signal WB1 (to an L level), so that storage addresses AR1 and AR2 change correspondingly. Storage data WD1 and WD2 change as they are updated by data registers DReg.1 and DReg.2 that operate in response to activation of control signal WB2 (to an L level).
Read data register DReg.3 stores read data which correspond to the input address being input as a target of the reading operation and are selected by data path select circuit 170.
For memory array circuit 120, either the reading operation or the writing operation is performed depending on the signal level of write enable signal WE# in the relevant clock cycle. The memory cell targeted for the writing operation is the one that corresponds to the address signal that was input two clock cycles before.
In address matching circuit 160, the above-described address comparison circuits 30 and 32 perform matching of input address AR0 with storage addresses AR1 and AR2, respectively, in each clock cycle. Normally, at a cycle in which a reading operation is designated, data output from a memory cell corresponding to input address AR0 are transmitted to read data register DReg.3 via path 1, and are output from data terminal 19 as output data.
However, if address matching circuit 160 detects that at least one of storage addresses AR1 and AR2 matches input address AR0, i.e., when at least one of address match signals EQ1 and EQ2 is activated (to an H level), any one of paths 2 to 4 is established instead of path 1. In this case, transmitted to read data register DReg.3 as a target of the reading operation is not the read data from the memory array circuit, but storage data WD1, WD2, or the write data input to the data terminal at the relevant clock cycle.
As explained above, conventional semiconductor memory device 5000 employs a pipeline operation to perform the reading/writing operations for the memory cell array and the data input/output operations at the data terminal independent of each other. However, it is necessary to constantly check the correlation between the address corresponding to storage data that have temporarily been stored at the data retaining circuit but have not yet been written into the memory array circuit, and the address for which reading is newly designated. Thus, conventional semiconductor memory device 5000 is provided with address matching circuit 160.
This address matching circuit 160 of conventional semiconductor memory device 5000 is constantly held in an enabled state to perform matching between the input address and the storage address, regardless of which operation, reading or writing, is designated by the semiconductor memory device. This results in unnecessary power consumption.
In this conventional semiconductor memory device 5000, it is possible to omit an unnecessary writing operation to the memory array circuit in the case where a reading operation is to be performed immediately after the writing operation for the same address, for faster operation and reduced power consumption. However, in the case where writing operations are continuously designated for the same address, the device cannot omit a writing operation of the preceding data that is obviously unnecessary because the data will be overwritten immediately after the operation. This also causes unnecessary power consumption.
The present invention is directed to solve the above-described problems. An object of the present invention is to provide a synchronous semiconductor memory device employing a pipeline operation that consumes less power.
In summary, the present invention is a synchronous semiconductor memory device performing data input/output according to a control signal and an address signal, comprising a plurality of address terminals, a data terminal, a memory array circuit, a control circuit, a data retaining circuit, an address retaining circuit, an address select circuit, an address comparison circuit, and a read data select circuit.
The plurality of address terminals receive respective bits of an address signal. The data terminal inputs/outputs data. The memory array circuit performs reading of data from and writing of data to a plurality of memory cells arranged in rows and columns according to the address signal. The control circuit designates either a reading operation or a writing operation to the memory array circuit and also designates either data input or data output at the data terminal, according to the control signal at each clock cycle. The data retaining circuit, provided between the data terminal and the memory array circuit, takes in write data input to the data terminal at a clock cycle in which the data input is designated, and temporarily retains at least one piece of write data as storage data until it is written into the memory cell. The address retaining circuit receives the address signal from the plurality of address terminals, and retains at least one storage address signal corresponding to at least one piece of storage data. The address select circuit receives a read address signal being an address signal input to the address terminals for data output and a storage address signal, and selectively transmits one of the address signals to the memory array circuit, in response to the operation designated to the memory array circuit. The address comparison circuit performs matching between the read address signal and each storage address signal at a clock cycle in which the reading operation is designated. The read data select circuit responds to the matching result of the address comparison circuit, and selects one data from the write data, the storage data and the read data from the memory array circuit that corresponds to the read address signal. The read data latch circuit latches the data selected by the read data select circuit, and transmits the data to the data terminal at a clock cycle in which data output is designated.
According to another aspect of the present invention, a synchronous semiconductor memory device performing data input/output according to a control signal and an address signal comprises a plurality of address terminals, a data terminal, a memory array circuit, a control circuit, a data retaining circuit, an address retaining circuit, an address select circuit, an address comparison circuit, and a read data select circuit.
The plurality of address terminals receive respective bits of an address signal. The data terminal inputs/outputs data. The memory array circuit performs reading of data from and writing of data to a plurality of memory cells arranged in rows and columns, according to the address signal. The control circuit designates either a reading operation or a writing operation to the memory array circuit and also designates either data input or data output at the data terminal, according to the control signal at each clock cycle. The data retaining circuit, provided between the data terminal and the memory array circuit, takes in write data input to the data terminal at a clock cycle in which data input is designated, and temporarily retains at least one piece of write data as storage data until it is written into the memory cell. The address retaining circuit receives the address signal from the plurality of address terminals, and retains at least one storage address signal corresponding to at least one piece of storage data. The address select circuit receives a read address signal being an address signal input to the address terminals for data output and a storage address signal, and selectively transmits one of the address signals to the memory array circuit in response to the operation designated to the memory array circuit. The address comparison circuit performs matching of the storage address signals with the read address signal and a write address signal being an address signal input to the address terminals for data writing. In the case where the write address signal matches one of the storage address signals, the address comparison circuit cancels the writing operation of the storage data corresponding to the matched storage address signal to the memory array circuit. The read data select circuit responds to the matching result of the address comparison circuit, and selects one data from the write data, the storage data and the read data from the memory array circuit corresponding to the read address signal. The read data latch circuit latches the data selected by the read data select circuit, and transmits the data to the data terminal at a clock cycle in which data output is designated.
Therefore, a primary advantage of the present invention is that it is possible to provide a synchronous semiconductor memory device employing a pipeline operation that accomplishes high-speed data transfer with reduced power consumption, by allowing its address comparison circuit to operate only at the clock cycle in which a reading operation is designated, to determine if the reading operation is performed for the address retained in the address retaining circuit.
Another advantage of the present invention is that it is possible to provide a synchronous semiconductor memory device employing a pipeline operation that accomplishes high-speed data transfer with further reduced power consumption, by canceling, when the address retained in the address retaining circuit has become a target of another writing operation, the no longer necessary writing operation of the old write data to the memory array circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.